12.1 DC Electrical Specification

Vref[SC,Sys]

Inside the processor, the Vref[SC,Sys] signals have a large capacitance, and a low-pass filter at each receiver. The DCOk pins must not be asserted until there has been sufficient time for Vref[SC,Sys] to stabilize at each of the receivers inside the processor.

A typical Vref[SC,Sys] generator is two resistors which provide the Vref[SC,Sys] level associated with the chosen logic family, and a 10mF tantalum capacitor connected to the processor's Vref[SC,Sys] pin to provide stability.